This invention relates in general to non-volatile memory systems and, in particular, to a non-volatile memory system with programming time control.
The memory cells or charge storage elements (the two terms used herein interchangeably) of a non-volatile memory are typically programmed one partial or complete row of cells in parallel at a time. Programming voltage pulses are applied to the selected row of memory cells until the threshold voltage of each of the selected cells in the row has been programmed to a value within a predetermined voltage range (which may or may not be the final desired state of the cell) in a programming cycle. During each programming cycle, a time sequence of programming voltage pulses are applied at predetermined time intervals, such as periodic time intervals, where the amplitude of each programming pulse has been incremented by a fixed voltage step compared to the amplitude of the immediately preceding programming pulse in the sequence.
In time periods between the programming voltage pulses, program-verify operations are carried out. That is, the programmed level of each charge storage element being programmed in parallel is read after each programming pulse to determine whether it is not less than the verify voltage level to which it is being programmed. If it is determined that the threshold voltage of a given charge storage element has exceeded the verify voltage level, in a process referred to below as locking out, programming of such charge storage element is stopped by raising the voltage of the bit line to which the particular charge storage element is connected to from a low voltage (typically 0 volts) to a high or inhibit level (typically Vdd). Programming of other charge storage elements being programmed in parallel continues until they in turn reach their verify voltage levels. After each program verify operation, if there still is one or more charge storage elements being programmed in parallel whose threshold voltage still has not reached the verify voltage level, the amplitude of the programming pulse is increased by the predetermined step size and applied again to the charge storage elements being programmed in parallel, which is followed again by a program-verify operation. If after the next programming operation the increased programming pulse still has not caused the threshold voltage of all of the charged storage elements being programmed in parallel to reach the verify voltage level, the amplitude of the programming pulse is increased yet again by the same predetermined step size during the next time interval and this process is repeated until threshold voltages of all of the charge storage elements being programmed in parallel have reached the verify voltage level. This marks the end of a particular programming cycle.
In a floating gate charge storage element in which charge is introduced by Fowler-Nordheim tunneling, the amount of charge on the floating gate can be calculated as a function of the voltage pulse characteristics using well know tunneling equations. FIG. 5A shows the threshold voltage (measured from the control gate) as a function of the number of voltage pulses applied to the control gate. The various Fowler-Nordheim parameters used in this simulation were chosen to be typical of a 90 nm NAND process, and the voltage pulse was assumed to start at 15 volt and increase by 0.2 volts for every pulse. The two curves show that for two different pulse durations (10 μsec and 15 μsec), the slope of the threshold vs. voltage is nearly the same. The longer pulse duration produces an initially higher threshold voltage (more charge tunnels during the longer time) but the change in threshold with each pulse is proportional to the absolute value of the voltage. This means that as long as we use a fixed pulse duration for each programming step, we can expect that during each pulse the threshold will increase no more than a given amount (in this case 0.2 volts), and if we inhibit programming on a cell by cell basis as described above we expect the final threshold distribution of all cells programmed to a given logic state to be within a narrow range approximately equal to the voltage pulse step size.
The problem observed is that if the pulse duration is allowed to vary during a programming sequence, the width of that threshold distribution will be undesirably larger. FIG. 5B shows a simulation in which the first 4 pulses are applied at a constant program duration of 10 μsec with each pulse increasing by 0.2 volts, and then followed by a variable program pulse width. Series 1 shows the change in threshold voltage in the case that the 5th and all subsequent pulses are 15 μsec. After another 5–10 pulses, the change in subsequent threshold voltage approaches that obtained previously with the narrower pulse, in accordance with the results shown in FIG. 5A. Note that even one longer pulse can increase the threshold of any cells locked out after that pulse such that they may exceed that expected if the pulse width did not increase. Series 2 shows the expected change in threshold voltage in the case where the pulse duration oscillates between 10 μsec and 15 μsec after each pulse: pulse 5 is 10 μsec and pulse 6 is 15 μsec, pulse 7 is 10 μsec and pulse 8 is 15 μsec and so forth. In this case the threshold distribution of the programmed state will be larger than that obtained by applying either 10 μsec or 15 μsec consistently, or that obtained from a one time change in pulse width. Although some pulses result in less than 0.2 volt threshold voltage change, that is not necessarily helpful because if that pulse fails to lockout but is right below the verify level, it will simply require one more pulse whose expected threshold change is larger resulting in a widened threshold distribution.
The above programming operation applies both to multi-level charge storage elements as well as binary-level charge storage elements or memory cells. An illustration of the above programming and program-verify operations to multi-level charge storage elements is described in U.S. Pat. No. 6,522,580, which is incorporated herein by reference in its entirety.
As will be evident from the above description, the above programming process requires repetitively programming the cells with a programming pulse followed by a program-verify operation. This process, therefore, can be time consuming. It is, therefore, desirable for the program time for the application of each programming pulse to have a short duration so that the memory cells or charge storage elements can be programmed to the desired threshold voltages in as short a time as possible for improved performance.
The programming pulses for programming the memory cells are often generated by charge pumps in which the output voltage is easily changed via DAC control. The voltage output of the charge pump is typically compared to a reference voltage. When the output of the charge pump reaches the value of the reference voltage, a program flag signal FLGPGM is generated to indicate that the pump output voltage has reached the desired program voltage level. The measurement of the programming time for the selected cells in the selected row will start as soon as the program flag FLGPGM is high. When this programming time starts, the programming voltage output (also called pump pulse) of the charge pump is applied to the memory cells or charge storage elements in parallel for altering their threshold voltages. In the event that the program flag FLGPGM is delayed, such as where the charge pump is weak as described below, programming will start at a predetermined time after the expected time of flag FLGPGM when the program flag FLGPGM has not yet arrived, resulting in a variable program duration from pulse to pulse.
When the program voltage level is increased by a certain step size voltage, the reference voltage is increased by the same step size and used for comparison with the programming pulse after it has been increased in step size. In this manner, the reference voltage that is used for generating the program flag FLGPGM will keep in step with the increasing program voltage level.
The strength of many charge pumps is a function of both temperature and input voltage level. At cold temperatures, for example, some types of charge pumps tend to be weak so that they require more time for the output voltage of the charge pump to reach a particular expected voltage value. Weak charge pumps may also take longer to provide a voltage output where a high amplitude voltage output is called for compared to where a low amplitude voltage output is required. Therefore, when the pump is weak so that the program flag FLGPGM is delayed, programming will start at periodic times even when the programming voltage pulse amplitude has not reached its intended or expected value. It is observed that under such circumstances, within a programming cycle, real programming is triggered sometimes by the arrival of the program flag FLGPGM, and sometimes at periodic times when the program flag FLGPGM is delayed. The effective programming time (the portion of the programming time period during which the programming pulse is at the desired voltage level) will therefore vary. This can cause a broadening of the threshold voltage distribution of the memory cells.
One solution is to increase the time allotted for the programming, so that even though at the beginning of the programming time period the voltage output of the charge pump has not yet reached the desired voltage level, the longer programming time period allocated for programming allows a weak charge pump to reach a desired voltage level after a certain time delay, so that the resulting effective programming time will still be adequate for programming the memory cells to the intended threshold voltage value. However, as noted above, for increased performance it would be desirable to minimize the programming time in which the programming pulses are applied. Therefore, allocating a longer programming time would degrade the performance of the non-volatile memory system. This is particularly the case since the longer programming time is needed only under certain limited conditions. It is, therefore, desirable to provide a non-volatile memory system, where the above-described difficulties are alleviated.